1. Field of the Invention
The invention relates to integrated circuits, and more particularly, to integrated circuits used in information storage and retrieval.
2. Description of the Related Art
For over three decades the semiconductor industry has been able to take advantage of the technology scaling according to Moore's Law. A continual increase in memory chip density, and thus the on-chip memory capacity has enabled the development of new products such as portable electronic devices used for mobile computing and communications. Without high-density memory it would not have been possible to have devices such as cell phones, personal digital assistants (PDAs), palm-top computers, or even laptop computers. Power Consumption has become a significant factor in use of such portable devices. Power Consumption affects battery life, and lower power consumption leads to longer battery life. Static Random Access Memory (SRAM), has been an important component of portable devices since it consumes less power and is generally faster than dynamic RAM (DRAM) that requires periodic refresh operation to prevent loss of memory contents. Currently 16 Mb SRAMs and 256 Mb DRAMs are available on the market.
For portable device applications that require SRAM, low standby current is highly desirable so as to extend the battery lifetime. Otherwise, rapid depletion of the battery power can limit the use of portable devices and also can inconvenience users of those devices by requiring them to carry spare batteries, for example. In a present generation of portable devices, the typical standby current of a portable device is 5-10 microamperes (10−6 A). Ideally, the standby current would be zero, and the less the better. Standby current has several components, and one of the most significant components is due to leakage in memory cells. As the desired memory capacity for portable devices has grown, it is increasingly important to suppress the leakage current. Unfortunately, the leakage current in prior memory circuits tended to increase for each generation of technology scaling according to a physical law. It is well known that the subthreshold current of a Metal-Oxide Semiconductor (MOS) transistor increases exponentially as the device threshold voltage is scaled down as required for chip performance with a downscaled power supply voltage. This leakage current phenomenon in an MOS transistor is described generally in the following equation:Ileakage=K*exp ((Vgs−Vt)/(S/ln 10)) (1−exp(−Vds/VT))  (1)                where K is a constant that depends on the technology, Vgs is the gate-to-source voltage (=Vg−Vs), Vt is the device threshold voltage, S is the subthreshold voltage swing, VT is the thermal voltage (=kT/q) with k denoting the Boltzman's constant. S, the subthreshold swing voltage, can be described byS=(kT ln 10)/q*(1+Cd/Cox)  (2)        
Equation (1) suggests that an increase in Vt can be used to reduce the leakage current, and this approach is practiced reluctantly in VLSI design despite a speed penalty. In other words, increased Vt results in both reduced leakage current and increased signal propagation delay within the circuit. Thus, typically there has been a trade-off between a desire to minimize leakage current and a desire to maximize speed. This trade-off generally has been acceptable as long as reduced leakage current transistors with increased Vt are not in speed-critical paths. Ordinarily, transistors in speed-critical paths should have lower threshold voltages in order to ensure reduced signal propagation delay leading to increased circuit speed. However, lower threshold voltage can result in relatively heavy leakage currents in standby mode.
FIG. 1A is an illustrative circuit diagram of a known integrated circuit data storage cell of the type referred to as an SRAM cell. This prior SRAM cell includes six transistors, two transistors for access (m5, m6) and four transistors (m1, m2, m3, m4) for latching data with two cross-coupled inverters (m1-m3 pair and m2-m4 pair). Transistors m1-m4 serve as storage circuitry. In this example, the storage circuitry operates by latching data. Transistors m5 and m6 serve as access transistors for writing data to and reading data from the storage circuitry. Suppose, for example, that the stored data is logic “1.” The data-storing node X is set to high (“1”) and the other data-storing node X-bar is set to low (“0”). Therefore, transistors m1 and m4 are turned on while transistors m2 and m3 are turned off. Access transistors, m5 and m6, are turned on by driving wordline (WL) high and are turned off by driving wordline (WL) low. When m5 and m6 are turned on, BL is linked to node X and BL-bar is linked to X-bar.
More specifically, the integrated circuit data storage cell includes a latch circuit including first and second inverters. A first inverter includes a first high threshold voltage PMOS transistor m1 and a first high threshold voltage NMOS transistor m3 and a first data node X comprising interconnected source/drains (S/D) of the first PMOS m1 and NMOS m3 transistors. A second inverter includes a second high threshold voltage PMOS transistor m2 and a second high threshold voltage NMOS transistor m4 with a second data node X-bar comprising interconnected source/drains (S/D) of the second PMOS transistor m2 and NMOS m4 transistor. The gates of the first PMOS transistor m1 and first NMOS transistor m3 are coupled to the second data node X-bar. The gates of the second PMOS transistor m2 and the second NMOS transistor m4 are coupled to the first data node X. A first low threshold voltage access transistor m5 includes a first S/D coupled to the first data node X and to the gate of the second PMOS transistor m2 and to the gate of the second NMOS transistor m4 and includes a second S/D coupled to a first data access node A1 and includes a gate coupled to a first access control node C1. A second low threshold voltage access transistor m6 includes a first S/D coupled to the second data node X-bar and to the gate of the first PMOS transistor m1 and to the gate of the first NMOS transistor m3 and includes a second S/D coupled to a second data access node A2 and includes a gate coupled to a second access control node C2.
During a write operation, for example, when WL is high, data “1” on BL can be fed to node X by turning on access transistor m5, and at the same time, data “0” on BL-bar can be fed to node X-bar by turning on access transistor m6. The latching by m1-m3 and m2-m4 pairs enable stable storage of data “1” at node X even after the access transistors m5 and m6 are turned off with low voltage on WL line. Conversely, data “0” can be written to node X by providing logic “0” on BL while providing logic “1” on BL-bar when access transistors m5 and m6 are turned on by a high WL signal.
Conversely, during a read operation, both BL and BL-bar are pre-charged to a high voltage level, e.g., VDD. If the voltage level at node X-bar is low, then the voltage on BL-bar will discharge through m4. If the voltage level at node X-bar is high, then the voltage on BL-bar will not discharge through m4. Instead, the voltage of BL will discharge through m3. A sense amplifier (not shown) can sense a small voltage drop on either BL or BL-bar so as to determine the voltage level stored at nodes X and X-bar and generate an output signal, e.g. high when the stored data is high or low when the stored data is low.
Unfortunately, there have been reliability problems with this earlier SRAM cell. For instance, if m3 is leaky and conducts current from node X to ground, then the charge stored at that node can be reduced, pulling down the node voltage at X, which in turn can make m2 leak some charge into node X-bar. Voltage build up at node X-bar can in turn promote more leakage current through m3 potentially causing a transition to a new erroneous locked state. Thus, current leakage can result in reliability problems by causing erroneous data storage.
Another problem with the prior SRAM structure of FIG. 1A is that the voltage of a cell node can be influenced by bit line voltages during a read operation. For example, assume that the voltages of X and X-bar are high and low respectively, and BL and BL-bar are precharged at VDD. When WL is enabled, m5 and m6 become to turned on. Node X at the junction of m1 and m3 is coupled to BL, and node X-bar at the junction of m2 and m4 is coupled to BL-bar. Since BL-bar is precharged to VDD and the level of X-bar is low (e.g., VSS), the voltage level on BL-bar can influence the voltage level at node X-bar. One approach to reducing the influence that the voltage on BL-bar has on node X-bar is to increase the impedance of m6. However, increasing the impedance of m6 also slows down the read speed. Thus, there is a tradeoff between circuit stability and read speed.
In addition, leakage currents in standby mode can cause draining of the battery. FIG. 2 is an illustrative drawing of an I-V characteristics of a MOS transistor for two different threshold voltages (low Vt and high Vt). As explained by equation (1), the higher the threshold voltage, the lower the leakage current (Ids) in magnitude. Thus, design option “A” would use high Vt to lower the leakage current, but this would cause speed degradation since the signal propagation delay increases as Vt increases for a fixed Vgs (<VDD) swing. It is known that the propagation delay driven by a MOS transistor is inversely proportional to (Vgs−Vt). Thus, for a given Vgs, there is more delay at higher Vt. By comparison, design option “B” would use low Vt to increase speed by reducing signal propagation delay but leakage current can be reduced by making the transistor reverse-biased when the transistor is turned-off.
Although, the fact that leakage current can be reduced when a transistor is reversed-biased has been known, there still exists a need for an integrated circuit data storage cell that suppresses leakage current without performance degradation and reliability issues. In particular, there has been a need for an SRAM cell that reduces power consumption without sacrificing high speed performance.
There also has been a need for increased memory capacity within a given chip area. In order to store more information within a given area of a chip, the individual storage cell area should be small. For this reason, in the past, layout experts often did data storage cell layout manually. Even a tiny saving in the unit cell area can lead to significantly increased storage capacity within an overall chip area, especially when many data storage cells are used repeatedly on a chip. One approach that has been considered for increasing information storage capacity is to store more than one bit of data in a single memory cell. If two data bits can be stored in one unit cell, then effectively the memory capacity can be doubled for the same chip area. Moreover, the chip area for a given data storage capacity could be reduced, thus increasing the production yield. There has been a need for a memory cell architecture that allows a simple approach to implementing multiple-bit storage in a single memory cell.
In addition, there has existed a need to reduce power consumption due to precharging of bit lines for read operations and to reduce chip area occupied by precharge circuitry. FIGS. 1B-1D are illustrative circuit diagrams of showing the known cell of FIG. 1A coupled in a typical SRAM array structure in which each array has m-rows (WL) and n-columns (BL and BL-bar) of cells. Each column includes a bit line pair BL and BL-bar. Each array of FIGS. 1B-1D has a different known precharge circuitry configuration. More particularly, FIGS. 1B-1D show a first cell, cell-1 in a first column-1 and a last cell, cell-n of a last column-n of row m. Specifically, cell-1 and cell-n include respective input transistors m5 and m6 with gates coupled to WLm. Respective S/D terminals of m5 and m6 input transistors of cell-1 are respectively coupled to BL1 and BL1-bar. Respective S/D terminals of m5 and m6 input transistors are respectively coupled to BLn and BLn-bar.
FIG. 1B shows a first precharge circuitry configuration in which, at the end of each bit line, a precharge transistor, e.g., PMOS transistors mp1-1, mp1-2 mpn-1 and mpn-2, is placed to set the bit line (BL) and bit line bar (BL-bar) voltages at a certain level. For example, the notation “mp1-1” indicates, row-m, precharge, column-1, coupled to first bit line (BL1) of cell. For example, the notation “mpn-2” indicates, row-m, precharge, column-n, coupled to second bit line (BLn-bar) of the cell.
In the precharge circuitry configuration of FIG. 1B, all BL lines and all BL-bar lines are precharged to VDD through mp1-1, mp1-2, mpn-1 and mpn-2. The gates of these transistors are coupled to a power supply level, e.g., VSS in this example, and thus, the precharge transistors are always turned on, and the BL lines and BL-bar lines are continually precharged to VDD.
FIG. 1C shows a second precharge circuitry configuration similar to that of FIG. 1B. However in the configuration of FIG. 1C the precharge transistors are controlled by a precharge control signal PPRE.
FIG. 1D shows a third precharge circuitry configuration in which each bit line pair has a dedicated control signal, e.g., PPRE1 for BL1 and BL1-bar and PPREn for BLn and BLn-bar. These dedicated control signals permit selective precharging of bit pairs. Selective precharging can reduce power consumption since current paths not involved in a read operation are not unnecessarily precharged. Moreover, cells in a given SRAM array can be divided into groups, and different respective precharge signals can be used to control precharging of different respective groups of cells. For example, assuming that there are 128 cells in an SRAM array, and that only 16 bits of cell data are read at a time, then the cells of the array can be divided into 8 groups, and each group can have a different precharge control signal.
While a precharge circuitry configuration such as that of FIG. 1D can reduce precharge-related power consumption, there has existed a need for further improvements in precharge-related power consumption and for precharge circuitry that occupies less chip area.
The present invention meets these needs.